Basic VHDL Program with testbench in SystemVerilog for a Zybo Board

 The FPGA code toggles a user LED in Zybo Board, the speed of which is controlled by 2 toggle switches. Codes can be downloaded from the below link.

https://github.com/kola-uhas/FPGA-codes/tree/main

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hello is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           speed_sw : in STD_LOGIC_VECTOR (1 downto 0);
           led : out STD_LOGIC);
end hello;
architecture Behavioral of hello is
signal led_toggle : std_logic := '0';
signal count : unsigned (7 downto 0):= (others => '0');
constant prescaler_val : unsigned (7 downto 0) := to_unsigned(49,8); --decimal value is 50 
signal slower_clk:  std_logic := '0';
signal led_toggle_count: unsigned (19 downto 0) := (others => '0'); 
signal speed_val_index: std_logic_vector(2 downto 0);
type speed_val_array is array (3 downto 0) of unsigned(19 downto 0);
signal speed_val : speed_val_array := (to_unsigned(99000,20),to_unsigned(249000,20),to_unsigned(499000,20),to_unsigned(999000,20));
begin
    clk_div: process(clk,rst)
    begin
        if rising_edge(clk) then
            if rst = '1' or count = prescaler_val then
                count <= (others => '0');
                slower_clk <= not slower_clk;
            else
                count <= count + 1;
            end if;
        end if;
    end process;
    
    led_toggle_logic : process(slower_clk)
    begin
        if rising_edge(slower_clk) then
            if led_toggle_count = speed_val(to_integer(unsigned(speed_sw))) then
                led_toggle_count <= (others => '0');
                led_toggle <= not led_toggle;
            else
                led_toggle_count <= led_toggle_count + 1;
            end if;
        end if;
    end process;
led <= led_toggle;
end Behavioral;

Following is the System Verilog testbench

`timescale 1ns / 1ps
module tb_hello;
logic clk = 0;
logic rst = 1;
logic [1:0] speed_sw = 2'd0;
logic led;
hello dut (
.clk (clk),
.rst (rst),
.speed_sw(speed_sw),
.led(led)
);
always #10 clk = ~clk;
initial begin
#100 rst = 1;
#400 rst = 0;
#500 speed_sw = 2'd1;
#2000000 speed_sw = 2'd2;
#4000000 speed_sw = 2'd3;
#5000000 $finish;
end
endmodule